The VDPU is an ASIC built for vector retrieval in retrieval-augmented generation and agentic AI workloads, also offered on an accelerator card. It integrates with Dnotitia’s own Seahorse vector database and with FAISS, Milvus and hnswlib.
On an FPGA evaluation platform, a four-card VDPU server reached up to 5.77 times the vector-search throughput of a dual-socket CPU-only server with equal or better recall. On a 4,096-dimensional multimodal workload the company measured host CPU use during index building reduced by 92 percent and host memory reduced by 73 percent. The ASIC target is up to 10 times vector-search performance against a CPU-based server.
Dnotitia states plainly that all performance figures were measured on the FPGA platform and do not represent final ASIC performance. First-generation ASIC samples have returned from fab and chip-level characterisation is underway, with ASIC-based evaluations planned to begin in the fourth quarter of 2026.
5.77 times faster, measured by the company against its own baseline
What the release does not contain is as relevant as what it does. There are no independent benchmarks, no ASIC measurements, no power or efficiency data, no pricing, no named customers and no named system or database partners. The release refers to prospective customers and ongoing discussions.
For SaaS companies the useful part is not the chip. It is the implied claim about where the cost sits.
Retrieval has been treated as the cheap half of RAG and generation as the expensive half. A company building dedicated silicon for the retrieval step is betting that at scale the search, the index build and the memory pressure around them are a large enough line item to justify separate hardware.
That is a question any RAG-heavy product can answer about itself without buying anything. Separate the monthly infrastructure bill into embedding, index maintenance, vector search and model calls. Most teams have never split it, and the result decides whether specialised retrieval hardware is ever going to be relevant to them.
If generation dominates, the chip is irrelevant and the work belongs in prompt and model selection. If index building and search dominate, the cheaper intervention is usually still software: smaller dimensions, better filtering, tiered indexes or simply retrieving less.
Dedicated silicon becomes interesting only for products with sustained, high-volume retrieval and a margin that infrastructure genuinely constrains. Even then, the realistic timeline is the Q4 2026 ASIC evaluation at the earliest, and the first independent numbers will matter more than any vendor figure published so far.
More information
Source and more information: Dnotitia Brings Dedicated Vector Silicon to Server Scale at AI Infra Summit 2026